1. Field of the Invention
The present invention relates to a test circuit, and in particular, relates to a test circuit for a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional test circuit for a semiconductor integrated circuit disclosed by Japanese Kokai Tokkyo Kohou H10-267994 (D1) which corresponds to U.S. Pat. No. 6,073,260. This test circuit is to test logic blocks 1, 3, 5 and comprises scanning flip-flop (SFF) circuits 10-1 and 10-2 and a selector 6. A scanning input data SIN, which is a data for testing the logic blocks 10-1 and 10-2, is supplied from a scanning data input terminal 10. A clock signal CLK is supplied from a clock signal input terminal 11 to clock terminals of the SFF circuits 10-1 and 10-2. A mode designation signal MOD is supplied from a mode designation signal input terminal 12 to mode selection terminals SE of the SFF circuits 10-1 and 10-2. Scanning output data, which are logic signals generated from the logic blocks 1, 3, and 5, are output from a scanning output terminal 13. This test circuit sequentially inputs the scanning input data SIN which are data for testing the logic blocks 10-1 and 10-2 from the scanning data input terminal 10 and sequentially outputs scanning output data SOUT which are resultant logic signals generated from logic blocks 1, 3, and 5 in response to the scanning input data SIN. It is possible to examine operations of the logic blocks 1, 3, and 5, for example, by comparing the scanning output data SOUT with expected data.
As shown in FIG. 1, the scanning input terminal 10 is connected to a scanning input terminal SI of the SFF circuit 10-1 through a scanning path 1S and an input terminal IN of the logic block 1. An output terminal OUT of the logic block 1 is connected to an input terminal D of the SFF circuit 10-1. An output terminal of the SFF circuit 10-1 is connected to a scanning input terminal SI of the SFF circuit 10-2 through a scanning path 3S and to an input terminal IN of the logic block 3. An output terminal OUT of the logic block 3 is connected to an input terminal D of the SFF circuit 10-2. An output terminal Q of the SFF circuit 10-2 is connected to the selector (SEL) 6 through a scanning path 5S and an input terminal IN of the logic block 5. An output terminal OUT of the logic block 5 is connected to the SEL 6. An output terminal of the SEL 6 corresponds to the scanning output terminal 13. The clock signal input terminal 11 is connected to clock terminals of the SFF circuits 10-1 and 10-2. The mode designation signal input terminal 12 is connected to mode selection terminals SE of the SFF circuits 10-1 and 10-2 and the selector SEL circuit 6.
The D1 further discloses the SFF circuit which is provided with a first FF circuit, a selector circuit, and a second FF circuit. The first FF holds a data at a timing of an inversed clock signal. The selector circuit inputs a data from either the logic block or the first FF circuit and outputs the data. The second FF holds the data supplied from the selector circuit at a timing of the clock signal CLK.
However, there are some problems in the conventional test circuit for a semiconductor integrated circuit of FIG. 1. One of the problems is that the conventional test circuit is only applicable to a simple logic block having only one input-output terminal for testing. As stated above, the typical logic block mounted on the semiconductor integrated circuit is provided with plural input-output terminals, and thus performs plural logic operations. There is a possibility that the conventional test circuit is inadequate for testing such a complex logic block that has plural input-output terminals and performs plural logic operations at the same time. Therefore, there is a problem of reliability of the conventional test circuit.